Employment

• Transistor/Interconnect Process/Device Development Engineer (Intel Corporation)
   Hillsboro, Oregon, USA (2020 Mar. - Present)

• Graduate Lab Research Assistant (Purdue University)

Advisor: Peide D. Ye (2016 May - 2019 May)

• Graduate Lab Teaching Assistant (Purdue University)

ECE 208 - Electronic Devices and Design Laboratory (2015 Aug. - 2018 May)

• Graduate Research Assistant (KAIST)

Nano IC Technology Laboratory (nit.kaist.ac.kr) (2012 Feb. - 2014 Feb.)

• Republic of Korea Air Force (Military Service)

Generator/Substation maintenance, Power management division (2006 Mar. - 2008 May)

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Education

Purdue University, College of Engineering (2015 - 2019)

PhD Major: Department of Electrical and Computer Engineering (2015.8.24 ~ 2019.12.15)

Research interest: Research on high performance Germanium Fin/Nanowire FET devices.

Advisor: Prof. Peide, Ye (https://engineering.purdue.edu/~yep/)

This video was taken at Purdue University and I was recorded in the video as well. You can see me from 0:20.

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KAIST, College of Engineering (2012 - 2014)

M.S Major: Department of Electrical Engineering

GPA: 4.25/4.30 (GPA Rank 3 out of 138 in the department, 6 out of 949 in the graduate school)

Thesis: Research on improvement of electrical properties of Ge pMOS devices using Vacuum Annealing and Ultrathin Hf layer with sub-1nm EOT. (Project with Samsung Electronics, System LSI Division)

Advisor: Prof. Byung Jin, Cho (https://need.kaist.ac.kr/), Committee: Prof. Hee Chul Lee and Yang Kyu Choi

 

This video shown below was taken while I was at KAIST to be used as the official introductory video of KAIST and was shown at American Society for Engineering Education conference. 

You can see me conducting experiment in National NanoFab center from 4:47 and also watch my interview at 5:06 of the video. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hanyang University, College of Engineering (2005 - 2012)

Department of Electronic and Computer Engineering

 

GPA: 4.38/4.5 (GPA Rank 1 out of 160 students in the department)

Graduation Project:

Android, Bluetooth-controlled Bicycle wheel tuning using LED POV display

http://youtu.be/58xfEayH7WU

 

The video includes English subtitles. Select [Subtitles/CC] to view it.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Publications

Conference

[13] Mengwei Si, Yandong Luo, Wonil Chung, Hagyoul Bae, Dongqi Zheng, Junkang Li, Jingkai Qin, Gang Qiu, Shimeng Yu, Peide D. Ye, “A Novel Scalable Energy-Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor Junction,” International Electron Devices Meeting (IEDM), San Francisco, USA, December 7-11, 2019.

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[12] Hagyoul Bae, Mengwei Si, Jinhyun Noh, Gang Qiu, Adam R. Charnas, Wonil Chung, Xiao Lyu, Sami Alghamdi, and Peide D. Ye, “Atomic Layer Deposited Ultrathin and Transparent Cu2O-based Solar Blind Ultraviolet Light Photodetector with a Novel Copper Precursor,” in 50th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, USA, December 12-14, 2019.

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[11] Wonil Chung, Mengwei Si, and Peide D. Ye, “Observation of Anomalous Bias Temperature Instability in Hf0.5Zr0.5O2-based Germanium Ferroelectric Nanowire pFETs,” in 49th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, USA, December 6-8, 2018.

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[10] Wonil Chung, Mengwei Si, and Peide D. Ye, “First Demonstration of Ge Ferroelectric Nanowire FET as Synaptic Device for Online Learning in Neural Network with High Number of Conductance State and Gmax/Gmin,” International Electron Devices Meeting (IEDM), San Francisco, USA, December 1-5, 2018

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[9] Sami Alghamdi, Wonil Chung, Mengwei Si, and Peide D. Ye, “Time Response of Polarization Switching in Ge Hafnium Zirconium Oxide Nanowire Ferroelectric Field-effect Transistors,” Device Research Conference (DRC), Santa Barbara, USA, June 24-27, 2018.

 

[8] Wonil Chung, Mengwei Si, and Peide D. Ye, “Alleviation of Short Channel Effects in Ge Negative Capacitance pFinFETs,” Device Research Conference (DRC), Santa Barbara, USA, June 24-27, 2018.

 

[7] Mengwei Si, Wonil Chung, Gang Qiu, Jinhyun Noh, and Peide D. Ye, "Anti-Ferroelectric Hafnium Zirconium Oxide Enhancement on MoS2 Negative Capacitance Field-effect Transistor Gate Stack," IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, USA, June 17-18, 2018.

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[6] Wonil Chung, Mengwei Si, Pragya R. Shrestha, Jason P. Campbell, Kin P. Cheung, Peide D. Ye, "First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs", Symposia on VLSI Technology and Circuits (Late News), Honolulu, USA, June 18-22, 2018.

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[5] Wonil Chung, Heng Wu, Mengwei Si, and Peide D. Ye, “Experimental extraction of Ballistic Efficiency of Germanium Nanowire NMOSFETs,” in 48th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, USA, December 6-9, 2017.

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[4] Wonil Chung, Mengwei Si, and Peide D. Ye, "Hysteresis-free Negative Capacitance Germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec," International Electron Devices Meeting (IEDM), San Francisco, USA, December 4-6, 2017.

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[3] Mengwei Si, C. Jiang, C.-J. Su, Y.-T. Tang, Lingming Yang, Wonil Chung, M. A. Alam, and Peide D. Ye, "Sub-60 mV/dec Ferroelectric

HZO MoS2 Negative Capacitance Field-effect Transistor with Internal Metal Gate: the Role of Parasitic Capacitance ," International Electron Devices Meeting (IEDM), San Francisco, USA, December 4-6, 2017.

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[2] Yunsang Shin, Wonil Chung, Yusin Seo, Choongho Lee, Dongkyun Sohn and Byung Jin Cho, “Demonstration of Ge pMOSFETs with 6 A EOT using TaN/ZrO2/Zr-cap/n-Ge(100) Gate stack Fabricated by Novel Vacuum Annealing and in-situ metal capping method,” Symposium on VLSI Technology (VLSI), Honolulu, USA, June 9-13, 2014.

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[1] Wonil Chung, Yunsang Shin, Choongho Lee, Dongkyun Sohn, and Byung Jin Cho, “In-situ Hafnium capping process for 0.6 nm EOT on Ge Wafer,” The 21st Korean Conference on Semiconductors (KCS), Seoul, Republic of Korea, February 24-26, 2014.

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Journal

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[9] Dongqi Zheng, Wonil Chung, Zhizhong Chen, Mengwei Si, Calista Wilk and Peide D. Ye, “Controlling Threshold Voltage of CMOS SOI Nanowire FETs with Sub-1-nm Dipole Layers Formed by Atomic Layer Deposition,” IEEE Transactions on Electron Devices (TED), vol. 69, no. 2, pp. 851-856, 2022.

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[8] Hagyoul Bae, Tae Joon Park, Jinhyun Noh, Wonil Chung, Mengwei Si, Shriram Ramanathan and Peide D. Ye, “First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors,” Nanotechnology, vol. 33, no. 12, 2021.

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[7] Hagyoul Bae, Adam Charnas, Wonil Chung, Mengwei Si, Xiao Lyu, Xin Sun, Haiyan Wang, Dmitry Zemlyanov, and Peide D. Ye, “Ultrathin Transparent Copper(I) Oxide Films Grown by Plasma-Enhanced Atomic Layer Deposition for BEOL p-Type Transistors,” Nano Express, vol. 2, no. 2, 2021.

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[6] Jinhyun Noh, Hagyoul Bae, Junkang Li, Yandong Luo, Yiming Qu, Tae Joon Park, Mengwei Si, Xuegang Chen, Adam R. Charnas, Wonil Chung, Xiaochen Peng, Shriram Ramanathan, Shimeng Yu, and Peide D. Ye, “First Experimental Demonstration of Robust HZO/β-Ga2O3 Ferroelectric Field-Effect Transistors as Synaptic Devices for Artificial Intelligence Applications in a High Temperature Environment,” IEEE Transactions of Electron Devices (TED), vol. 68, no. 5, p. 2515-2521, 2021.

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[5] Mengwei Si, Zehao Lin, Jinhyun Noh, Junkang Li, Wonil Chung, Peide D. Ye, “The Impact of Channel Semiconductor on the Memory Characteristics of Ferroelectric Field-Effect Transistors,” Journal of the Electron Devices Society, vol. 8, pp. 846-849, 2020.

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[4] Hagyoul Bae, Adam R. Charnas, Xing Sun, Jinhyun Noh, Mengwei Si, Wonil Chung, Gang Qiu, Xiao Lyu, Sami Alghamdi, Haiyan Wang, Dmitry Zemlyanov, Peide D. Ye, “Solar-blind UV photodetector based on atomic layer deposited Cu2O and nano-membrane β-Ga2O3 pn oxide heterojunction,” ACS Omega, vol. 4, pp. 20756-20761, 2019.

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[3] Wonil Chung, Heng Wu, Wangran Wu, Mengwei Si, and Peide D. Ye, “Experimental Extraction of Ballisticity in Germanium Nanowire nMOSFETs,” IEEE Transactions on Electron Devices (TED), vol. 66, no. 8, pp. 3541–3548, Aug. 2019.

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[2] SangHoon Shin, Hai Jiang, Woojin Ahn, Heng Wu, Wonil Chung, Peide D. Ye, and Muhammad Ashraful Alam, “Performance Potential of Ge CMOS Technology From a Material-Device-Circuit Persperctive,” IEEE Transactions of Electron Devices (TED), vol. 65, no. 5, p. 1679-1684, 2018.

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[1] Mengwei Si, Chunsheng Jiang, Wonil Chung, Yuchen Du, Muhammad A. Alam, and Peide D. Ye, “Steep-slope WSe2 Negative Capacitance Field-effect Transistor,” Nano Letters, vol. 18, no. 6, 2018.

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Book

[1] Wonil Chung, Heng Wu, and Peide Ye, “Integration of Germanium into Modern CMOS: Challenges and Breakthroughs,” in Advanced Nanoelectronics, Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2018, pp. 91–117.

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Research/Project Experiences (Graduate & Undergraduate)

Graduate

• Silicon (SOI) / Germanium (GeOI) based CMOS Fin/Nanowire FET devices​​​​ (2015 - 2019)

Tools: E-beam Lithography (JEOL JBX-8100FS, VISTEC VB6, VISTEC EBPG5200), Photolithography (Karl Suss MJB-3, MJB4), E-beam Evaporator (CHA, PVD systems), Plasma RIE Etcher (Panasonic E620), RTA (Jipelec, Minipulse), Tube Furnace (Protemp), Thermal/Plasma Metal and Oxide ALD (Arradiance XT4/XT8, F120), SEM (Hitachi S4800)

 Industry projects: Lam research USA (2016 ~ 2017), Samsung Advanced Logic Lab (2018 ~ 2019)

• Development of high mobility Ge MOSFET logic devices beyond 15nm technology node (2012 - 2014)

Reduction of Hysteresis and Leakage current by incorporation of Hf metal to HfO2-based Ge pMOS gate stack at sub-1nm EOT range (Funded by Samsung Electronics)

• Maintenance experiences in semiconductor fabrication facilities (2012 - 2014)

i) Jusung EUREKA-3000 Atomic Layer Deposition (ALD) System

ii) AJA RF, DC Magnetron Metal Sputtering System

 

Undergraduate

• Electronics Projects

i) Designed and implemented Persistence of Vision Display with a Bluetooth communication system and displayed RPM/Speed of a bicycle wheel (2011)

ii) Designed cooling fan control with temperature sensor and an ATMEGA16 microcontroller (2009)

• Display Driving Circuit Design and fabrication

i) Implemented 8-bit Data Driving Circuit (Digital Block) for LCD using Cadence & Hspice tool (2011)

ii) IPS panel redesign project by optimization of metal patterns using TechWiz LCD Simulator (2011)

• Digital Signal Processing Project

i) Designed FIR/IIR filter with MATLAB (2010)

• RF Design Project

ii) Designed Quadrature Hybrid with HFSS v.11 (2010)

 

Honors and Awards

• Bilsland Dissertation Fellowship (2019)

• Estus H. and Vashti L. Magoon award for excellence in Teaching (2015~2016)

  • https://engineering.purdue.edu/ECE/Spotlights/graduate-students-receive-magoon-awards​

• Full Scholarship from Jeongsong Cultural Foundation (3 years), 2015 - 2018

  • http://www.jeongsong.co.kr/​

• KAIST Graduate school Scholarship (4 semesters) 2012 - 2014

• Hanyang English Presentation Contest for Engineering students – 1st Award, 2011

• 1st Award in Graduation Project Competition (Department of Electronic Engineering), 2011

• 1st Award in Capstone Design Fair (School of Engineering, Hanyang University), 2011

- Android, Bluetooth-controlled Bicycle wheel tuning using LED POV display

• Full Scholarship, Korean Government, Korea Student Aid Foundation (4 consecutive semesters) 2010 - 2011

• Full Scholarship, Hanyang University (3 consecutive semesters excluding military service period) 2005, 2009

• 1st Award in ‘Overseas Research & Study for Youth’ from the Ministry of Health and Welfare of Republic of Korea, 2009

Thesis: Sustainable and eco-friendly technologies of Northern Europe and possible adaptations to Korea

 

Language

• Language tests

     i) Fluent in English (TOEFL: 116, GRE: Verb. 160/Quant. 170/Writing 4.0)

     ii) Chinese Character Ability Test (Level 2, 136 points out of 150)

     iii) Worked as a Phone English teacher for CES English (2008)

• Overseas experience

     i) Singapore: Dec. 1995 – Aug. 2000

Singapore Korean School (Elementary School)

Singapore American School (Middle School)

     ii) USA: Jul. 2015 – Present

Purdue University (Graduate School)

 

Extra-curricular experiences

• Backpacking Travel experiences – Have been to more than 30 countries (2005 - Present)

• Supporter of 2 children at World Vision – (2009 - Present)